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exar corporation, 48720 kato road, fremont, ca 94538 (510) 668-7000 fax (510) 668-7017 www.exar.com xrd98l23 8-bit, high-speed linear cis/ccd sensor signal processor with serial control november 2002-2 features 8-bit resolution, no missing codes one-channel 10msps pixel rate dual-channel 5msps pixel rate three-channel 3 msps pixel rate 6-bit programmable gain amplifier 8-bit programmable offset adjustment cis or ccd compatibility internal clamp for cis or ccd ac coupled configurations 3.3v operation & i/o compatibility serial load control registers low power cmos: 75mw-typ low cost 20-lead packages usb compliant applications check scanners general purpose cis or ccd imaging low cost data acquisition simple and direct interface to canon 600 dpi sensors ordering information package type temperature range part number 20-lead soic 0c to +70c xrd98l23acd 20-lead ssop 0c to +70c XRD98L23ACU general description the xrd98l23 is a complete linear cis or ccd sensor signal processor on a single monolithic chip. the xrd98l23 includes a high speed 8-bit resolution adc, a 6-bit programmable gain amplifier with gain adjust- ment of 1 to 10, and a typical 8-bit programmable input referred offset calibration range of 480mv. in the ccd configuration the input signal is ac coupled with an external capacitor. an internal clamp sets the black level. in the cis configuration, the clamp switch can be disabled and the cis output signal is dc coupled from the cis sensor to the xrd98l23. the cis signal is level shifted to vrb in order to use the full range of the adc. in the cis configuration the input can also be ac coupled similar to the ccd configuration. this enables cis signals with large black levels to be internally clamped to a dc reference equal to the black level. the dc reference is internally subtracted from the input signal. the cis configuration can also be used in other applications that do not require cds function, such as low cost data acquisition. rev. 1.00
xrd98l23 2 rev. 1.00 figure 1. functional block diagram red grn blu vdcext vref+ db7:0 dvdd dgnd avdd agnd adcclk clamp synch pga timing & control logic avdd 6-bit gain registers 8-bit adc rl agnd data i/o port buffer vrt vrb triple s/h & 3-1 mux 8-bit dac 8 8 8-bit offset registers 6 8 + _ agnd v dcref dc/ac int/ext_v dcref cis/ccd g<5:0> o<7:0> r g b r g b clp c l a m p power down power down vrt ccd cis vbg cis ref circuit cis ref circuit dc reference
xrd98l23 3 rev. 1.00 1 2 3 4 5 6 7 8 9 10 avdd vref+ xrd98l23acd 20 19 18 17 16 15 14 13 12 red grn blu vdcext agnd dvdd db0 db1 db2 db4 dgnd adcclk db3 11 db5/sclk db6/sdata db7/ld clamp synch 20-lead soic pin description pin # symbol description 1 dvdd digital vdd (for output drivers) 2 db0 data output bit 0 3 db1 data output bit 1 4 db2 data output bit 2 5 db3 data output bit 3 6 db4 data output bit 4 7 db5/sclk data output bit 5 & data input sclk 8 db6/sdata data output bit 6 & data input sdata 9 db7/ld data output bit 7 & ld 10 dgnd digital ground (for output drivers) 11 adcclk a/d converter clock 12 clamp clamp and video sample clock 13 synch start of new line and serial data input control 14 agnd analog ground 15 vref+ a/d positive reference for decoupling cap 16 vdcext external dc reference 17 blu blue input 18 grn green input 19 red red input 20 avdd analog power supply pin configuration
xrd98l23 4 rev. 1.00 electrical characteristics test conditions: av dd =dv dd =3. 3 v, adcclk=10mhz, 50% duty cycle, t a =25 c unless otherwise specified. symbol parameter min. typ. max. unit conditions power supplies av dd analog power supply 3.0 3.3 3.6 v dv dd digital i/o power supply 3.0 3.3 3.6 v dv dd < av dd i dd supply current (total) 25 60 ma v dd =3.0v idd pd power down power supply current 50 m a v dd =3.0v adc specifications res resolution 8 bits f s maximum sampling rate 12 msps dnl differential non-linearity 0.5 lsb inl integral non-linearity 1.0 lsb mon monotonicity yes v rt top reference voltage 2.1 2.2 2.6 v v rb bottom reference voltage av dd /10 v dv ref differential reference voltage 0.18 0.67av dd v (v rt - v rb ) r l ladder resistance 300 600 780 w pga & offset dac specifications pgares pga resolution 6 bits pgag min minimum gain 0.950 1.0 1.35 v/v pgag max maximum gain 9.5 10.0 10.50 v/v pgagd gain adjustment step size 0.14 v/v v black black level input adjust range -60 +300 mv dc configuration dacres offset dac resolution 8 bits off min minimum offset adjustment -180 -120 -80 mv mode 111, d5=0 (note 1) off max maximum offset adjustment +200 +360 +400 mv mode 111, d5=0 off min minimum offset adjustment -350 -240 -100 mv mode 111, d5=1 (note 1) off max maximum offset adjustment +100 +240 +350 mv mode 111, d5=1 off d offset adjustment step size 1.88 mv note 1: the additional 60 mv of adjustment with respect to the black level input range is needed to compensate for any additional offset introduced by the xrd98l23 buffer/pga internally.
xrd98l23 5 rev. 1.00 electrical characteristics (cont'd) test conditions: av dd =dv dd =3. 3 v, adcclk=10mhz, 50% duty cycle, t a =25 c unless otherwise specified. symbol parameter min. typ. max. unit conditions buffer specifications i il input leakage current 100 na cin input capacitance 10 pf vin pp ac input voltage range 0 av dd -1.4 v cis ac; int v dcref config reg => xxx010xx gain=1 (note 1) ac input voltage range 0 dv ref v ccd ac; int v dcref config reg => xxx011xx gain=1 (note 1) vin dc input voltage range -0.1 av dd -1.4 v cis dc; int v dcref config reg => xxx000xx gain=1 (note 2) dc input voltage range v dcext -0.1 v dcext + v cis dc; ext v dcref dv ref config reg => xxx100xx gain=1 (note 3) v dcext +dv ref < av dd v dcext external dc reference 0.3 av dd /2 v cis dc; ext v dcref config reg => xxx100xx vin bw input bandwidth (small signal) 10 mhz vin ct channel to channel crosstalk -60 db internal clamp specifications v clamp clamp voltage agnd 50 mv cis (ac) config 2.1 v rt v ccd (ac) config r int clamp switch on resistance 180 250 w r off clamp switch off resistance 12 m w note 1: vin pp is the signal swing before the external capacitor tied to the mux inputs. note 2: the -0.1v minimum is specified in order to accommodate black level signals lower than the external dc reference (clamp) voltage. note 3: the v dcext -0.1v minimum is specified in order to accommodate black level signals lower than the external dc reference voltage.
xrd98l23 6 rev. 1.00 electrical characteristics (cont'd) test conditions: av dd =dv dd =3. 3 v, adcclk=10mhz, 50% duty cycle, t a =25 c unless otherwise specified. symbol parameter min. typ. max. unit conditions system specifications (mux + buffer + pga + adc) note 1 sys dnl system dnl -1.0 0.5 +2.0 lsb no missing codes sys lin system linearity 6.0 lsb sys ge system gain error -5.0 +5.0 % irn input referred noise 1.5 mv rms gain=1 input referred noise 0.5 mv rms gain=10 system timing specifications tcklw adcclk low pulse width 50 ns tckhw adcclk high pulse width 50 ns tckpd adcclk period 100 ns tsypw synch pulse width 30 ns trars rising adcclk to rising 0 s ynch must rise equal to synch or after adcclk, see figure 18 tclpw clamp pulse width 30 ns note 2 write timing specifications tsclkw sclk pulse width 40 ns tdz ld low to sclk high 20 ns tds input data set-up time 20 ns tdh input data hold time 0 ns tdl sclk high to ld high 50 ns adc digital output specifications tap aperture delay ns tdv output data valid 30 50 ns tsa synch to adcclk (3ch) 20 ns 3ch pixel md tsa2 synch to adcclk (2ch) 20 80 ns 2ch pixel md tlat latency 8 cycles config 00, 11 tlat latency 6 pixels config 01, 10 digital input specifications v ih input high voltage av dd -1.5 v v il input low voltage 0.6 v i ih high voltage input current 5 m a i il low voltage input current 5 m a c in input capacitance 10 pf note 1: system performance is specified for typical digital system timing specifications. note 2: the actual minimum ?tclpw? is dependent on the external capacitor value, the cis output impedance. during ?clamp? operation, sufficient time needs to be allowed for the external capacitor to charge up to the correct operating level. refer to the description in theory of operation, cis config.
xrd98l23 7 rev. 1.00 electrical characteristics (cont'd) test conditions: av dd =dv dd =3. 3 v, adcclk=10mhz, 50% duty cycle, t a =25 c unless otherwise specified. symbol parameter min. typ. max. unit conditions digital output specifications v oh output high voltage 80 ( %) dvdd i l = 1ma v ol output low voltage 20 ( %) dvdd i l = -1ma i oz output high-z leakage current -10 10 m a c out output capacitance 10 pf sr slew rate (10% to 90% dv dd ) 2 15 ns c l = 10pf, dv dd = 3.3v
xrd98l23 8 rev. 1.00 theory of operation cis configuration (contact image sensor) the xrd98l23 has two configurations for cis applications. each configuration is set by the control registers accessed through the serial port. mode 1. dc coupled if the cis does not have leading or trailing black pixels as shown in figure 2, then dc couple the cis output to the xrd98l23 input. optically shielded pixels valid pixels adjust the offset of the cis (-60 mv to 300 mv) by setting the internal registers of the xrd98l23 to set the black pixel value when the leds of the cis are off. when the leds are on, use the xrd98l23 programmable gain to maximize the adcs dynamic range. figure 3 shows a typical application for a cis with an offset of -60mv to 300mv. figure 2. typical output cis mode
xrd98l23 9 rev. 1.00 r l vrt vrb vdd red xrd98l23 c i s m u x n/c n/c n/c the input is added to vrb before the signal passes through the adc. if the cis output is zero, then the output of the adc will be zero code. this enables the cis to be referenced to the bottom ladder reference voltage to use the full range of the adc. some cis sensors have an output with an offset voltage of greater than 300mv. if the cis output is beyond the offset range of the xrd98l23 (see offset control dac, pg. 27) set the internal mode registers to external reference. an external reference voltage equal to the value of the cis offset voltage can be applied to vdcext (figure 4) in order to meet the dynamic range of the xrd98l23. figure 4 is a diagram of the xrd98l23 in the external reference mode for cis, dc coupled applications. figure 3. application with offset in the range (-60mv to 300mv)
xrd98l23 10 rev. 1.00 rl vrt vrb vdd red xrd98l23 dc reference c i s m u x n/c n/c vdcext the dc reference voltage applied to vdcext does not have to be accurate. the internal offset dac voltage is still used in this mode for fine adjustment. vdcext cannot be used as an input from the cis. any signal applied to vdcext will be subtracted from the output signal of the multiplexer. figure 4. application with offset greater than (-60mv to 300mv)
xrd98l23 11 rev. 1.00 agnd dvdd (3v) vcc (5v - 15v) avdd dgnd avdd asic digital c i s n/c n/c 4 k 0 . 1 u f 0 . 0 1 u f 0.1uf 0 . 0 1 u f 0 . 1 u f 0 . 1 u f 1 k xrd98l23 dvdd 1 db0 2 db1 3 db2 4 db3 5 db4 6 db5/sclk 7 db6/sdata 8 db7/ld 9 dgnd 10 adcclk 11 clamp 12 synch 13 agnd 14 vref+ 15 vdcext 16 blu 17 grn 18 red 19 avdd 20 figure 5. typical application circuitry cis dc coupled non-inverted mode with vdc external offset compensation
xrd98l23 12 rev. 1.00 cis mode timing -- dc coupled (clamp disabled) adcclk tckhw tcklw tckpd tap tap pixel n-1 pixel n tdv pixel n+1 cis tdv [7:0] n-8 n/a n-7 n/a n-6 n/a n-5 n/a db figure 6. timing diagram for figure 5 adcclk events adc sample & pga start tracking next pixel data out - invalid data out hi adc track pga output lo adc hold/convert table 1. mode 2. ac coupled if the cis signal has a black reference for the video signal, an external capacitor c ext is used. when clamp (clamp) pin is set high an internal switch allows one side of the external capacitor to be set to ground. it then is level shifted to correspond to the bottom ladder reference voltage of the adc (figure 7).
xrd98l23 13 rev. 1.00 r l vrt vrb vdd xrd98l23 clamp rint red m u x c i s rext cext n/c n/c n/c therefore, tc =1/r int c ext if the input to the external capacitor has a source impedance (r ext ), then: t c =1/(r int +r ext )c ext this value corresponds to the black reference of the image sensor. when the clamp pin is set back to low, the adc samples the video signal with respect to the black reference. the typical value for the external capacitor is 100pf. this value should be adjusted according to the time constant (tc) needed in a particu- lar application. the clamp pin has an internal 180 ohm (from electrical tabels) impedance (r int ) which is in series with the external capacitor (c ext ). figure 7. cis ac coupled application
xrd98l23 14 rev. 1.00 dvdd (3v) avdd vcc (5v - 15v) dgnd agnd digital asic c i s n/c n/c n/c 100pf 0 . 1 u f 0 . 1 u f 0 . 0 1 u f 0 . 1 u f 0 . 0 1 u f xrd98l23 dvdd 1 db0 2 db1 3 db2 4 db3 5 db4 6 db5/sclk 7 db6/sdata 8 db7/ld 9 dgnd 10 adcclk 11 clamp 12 synch 13 agnd 14 vref+ 15 vdcext 16 blu 17 grn 18 red 19 avdd 20 figure 8. typical application circuitry cis ac coupled non-inverted
xrd98l23 15 rev. 1.00 cis mode timing -- ac coupled (clamp enabled) adcclk tckhw tcklw tckpd tap tap pixel n-1 pixel n tdv pixel n+1 cis tdv n-8 n/a n-7 n/a n-6 n/a n-5 n/a clamp tclpw db [7.0] figure 9. timing diagram for figure 8 adcclk events adc sample & pga start track of next pixel data out - invalid data out hi adc track pga output lo adc hold/convert table 2. clamp events hi pga tracks v clamp & c ext is charged to v black - v clamp , which is equal to v black lo pga tracks vin pp table 3.
xrd98l23 16 rev. 1.00 internal cis reference circuit (db 4 = 1) the xrd98l23 has an internal register reserved for interfacing to the canon cis model number cva- 60216k. when this register is selected, the vdcext (pin 16) becomes an output voltage of 1.24 volts. this voltage can be directly connected to the vref (pin 5) of the canon sensor. this reduces the amount of components needed for biasing the canon cis sensor (the external diodes and resistors typically used in this application have been included inside the xrd98l23 figure 10. typical application circuitry internal cis reference circuit mode canon cis sensor, model #cva=60216k for this mode of operation). below is a typical applica- tion circuit using the xrd98l23 and the canon cva- 60216k cis sensor. agn d dvdd (3v ) vcc (5v) avd d dgnd agn d dgnd dgnd dgnd dgnd dvdd (3v - 5v) asic digital n/c n/c canon cis sensor 0 . 1 u f 0 . 0 1 u f 0.1u f 0 . 0 1 u f 0 . 1 u f xrd98l23 dvdd 1 db0 2 db1 3 db2 4 db3 5 db4 6 db5/sclk 7 db6/ sdata 8 db7/ld 9 dgnd 10 adccl k 11 clam p 12 sync h 13 agn d 14 vref+ 15 vdcex t 16 blu 17 grn 18 red 19 avd d 20 cva-60216k vou t 1 mod e 2 agn d 3 vcc 4 vref 5 sp 6 clk 7 led com 8 led blu 9 led grn 10 led red 11 fgnd 12 1 0 k 1 0 k 1 0 k 47u f 4 7 u f npn npn npn 0.01u f 100u f
xrd98l23 17 rev. 1.00 cis line-by-line rotating gain and offset (configuration db1 = 1, db0 = 1) line-by-line rotating gain and offset minimizes the amount of write cycles per scan. pre-loaded values of gain and offset can be loaded for each color before the first line is scanned. each gain and offset is cycled through line-by-line so that the gain and offset do not have to be loaded in between lines. below is the typical application circuit and timing for this configuration. figure 11. typical application circuitry internal cis rotating gain and offset line-by-line avdd agnd dgnd vcc (5v - 15v) dvdd (3v) asic digital c i s n/c 0 . 0 1 u f 0 . 1 u f 0.1uf 0 . 1 u f xrd98l23 dvdd 1 db0 2 db1 3 db2 4 db3 5 db4 6 db5/sclk 7 db6/sdata 8 db7/ld 9 dgnd 10 adcclk 11 clamp 12 synch 13 agnd 14 vref+ 15 vdcext 16 blu 17 grn 18 red 19 avdd 20 0 . 0 1 u f
xrd98l23 18 rev. 1.00 ccd configuration (charge coupled device) mode 1. ac coupled in the ccd configuration of operation, an external capacitor needs to be chosen according to the equa- tions below. the typical value for the external capacitor is 100pf. this value should be adjusted according to the time constant (tc) needed in a particular applica- tion. the clamp pin has an internal 180 ohm imped- ance (r int ) which is in series with the external capacitor (c ext ). therefore, tc =1/r int c ext if the input to the external capacitor has a load imped- ance (r ext ), then t c =1/(r int +r ext )c ext when clamp (clamp) pin is set high an internal switch allows one side of the external capacitor to be set to vrt (figure 13). this value corresponds to the black reference of the ccd. when the clamp pin is set back to low, the adc samples the video signal with respect to the black reference. the difference between the black reference and the video signal is the actual pixel value of the video content. since this value is refer- enced to the top ladder reference voltage of the adc a zero input signal would yield a full scale output code. therefore, the output of the conversion is inverted (internally) to correspond to zero scale output code. figure 12. timing diagram for figure 11 cis rotating gain and offset line-by-line (md 11) adcclk cis synch gain/ offset ld red pixel line scan grn pixel line scan blu pixel line scan red gain/offset cycle grn gain/offset cycle blu gain/offset cycle reset internal mux color to red channel (ld = 110yyyyyy11) tsa tsypw note: y = previous state tri-state (synch = lo)
xrd98l23 19 rev. 1.00 area or linear ccd applications figure 13, is a block diagram for applications with area or linear ccds (the timing for area ccds and b/w ccds is the same). for area or linear ccd applica- tions, a global offset is loaded into the serial port at the beginning of a line. the gain is set to adjust for the highest color intensity of the ccd output. once the pixel values have been sampled, the gain and offset are adjusted at the beginning of the next line. for example, if there is a line-to-line variation between the black reference pixels, the offset is adjusted. the gain is always adjusted for the highest color intensity. figure 13. ccd ac coupled application rl vrt vrb vdd red xrd98l23 clamp m u x area or linear ccd n/c n/c n/c
xrd98l23 20 rev. 1.00 figure 14. typical application circuitry for a single channel b/w ccd ac coupled inverted mode dvdd (3v) avdd vcc (5v - 15v) dgnd agnd digital asic c c d n/c n/c n/c 100pf 0 . 1 u f 0 . 1 u f 0 . 0 1 u f 0 . 1 u f 0 . 0 1 u f xrd98l23 dvdd 1 db0 2 db1 3 db2 4 db3 5 db4 6 db5/sclk 7 db6/sdata 8 db7/ld 9 dgnd 10 adcclk 11 clamp 12 synch 13 agnd 14 vref+ 15 vdcext 16 blu 17 grn 18 red 19 avdd 20
xrd98l23 21 rev. 1.00 tdv tdv area, linear or b/w ccd -- ac coupled (clamp enabled) pixel n-1 pixel n pixel n+1 ccd channel n adcclk tckpd tap tap tckhw tcklw clamp tclpw n-8 n/a n-7 n/a n-6 n.a [7:0] db figure 15. timing diagram for figure 14 triple channel ccd application figure 16, is a block diagram for pixel-by-pixel applica- tions with triple channel ccds. during the optically shielded section of a pixel, clamp must go high to store the black reference on each capacitor to the input. the gain and offset is automatically rotated to adjust for each channel input. the data is available on the output bus on the falling edge of adcclk.
xrd98l23 22 rev. 1.00 rl vrt vrb vdd red/grn/blu xrd98l23 clamp c c d m u x n/c figure 16. ccd ac coupled application
xrd98l23 23 rev. 1.00 avdd vcc (5v - 15v) dgnd agnd digital asic c c d n/c 100pf 0 . 1 u f 0 . 1 u f 0 . 0 1 u f 0 . 1 u f 0 . 0 1 u f 100pf 100pf xrd98l23 dvdd 1 db0 2 db1 3 db2 4 db3 5 db4 6 db5/sclk 7 db6/sdata 8 db7/ld 9 dgnd 10 adcclk 11 clam p 12 synch 13 agnd 14 vref+ 15 vdcext 16 blu 17 grn 18 red 19 avdd 20 dvdd (3v) figure 17. typical application circuitry triple channel ccd ac coupled inverted mode
xrd98l23 24 rev. 1.00 (clamp enabled) blu grn red adcclk clamp data pixel-by-pixel 3 channel ccd -- ac coupled tdv red (n-6) n+1 pixel convert red (n) convert grn (n) convert blu (n) track red (n) track grn (n) track red (n+1) track blu (n) convert red (n+1) tdv tdv tdv tdv n/a grn (n-6) n/a blu (n-6) n/a clamp tsa synch tsypw tclp=10ns tap tclp=10ns n+1 pixel n+1 pixel n pixel n pixel n pixel simultaneous sample trars adcclk events 3rd simultaneous red/grn/blu sample every 3rd clk. convert red, s/h grn, s/h blu. all data out - non-valid data out hi adc track pga output lo adc hold/convert clamp events hi internal clamp enabled lo internal red/grn/blu tracking enabled synch events hi reset internal mux to red, output bus is tri-stated lo increment mux color on falling edge of adcclk table 4. figure 18. timing diagram for figure 17
xrd98l23 25 rev. 1.00 figure 19. timing diagram for 2-channel grn red adcclk data pixel-by-pixel 2-channel ccd tdv red(n_6) n+1 pixel convert red (n) convert grn (n) convert track red (n) track grn (n) track grn (n+1) track red (nh) convert grn (n+1) tdv tdv tdv tdv n/a grn(n-6) n/a red(n-5) n/a clamp tsa2 synch tsypw tap n+1 pixel n pixel n pixel simultaneous sample trars red (nh) tsypw
xrd98l23 26 rev. 1.00 t/h t/h t/h from ccd red channel from ccd grn channel from ccd blu channel 8-bit adc s1 s2 s3 s4 s5 s6 s7 s8 s9 adcclk clamp s4 and s5 open at this falling edge s6 opens, s7 closes at this rising edge s7 opens, s8 closes at this rising edge s8 opens, s4, s5 and s6 close at this rising edge track grn track blu track red track red convert red convert red convert grn convert blu ccd waveform s8 opens, s4, s5 and s6 close at this rising edge s9 closes at rising edge and opens at falling edge of adcclk s1, s2 and s3 close when clamp is high and open when clamp is low - + pga c ext r c ext g c ext b vcds = pgag * [v rt - (v rt - v pix )] = pgag * v pix xrd98l23 v rt - v rt v rt v pix v pix v pix v blk v blk - figure 20. cds timing (triple channel) mode: 110 00001110
xrd98l23 27 rev. 1.00 mode 2. dc coupled typical ccds have outputs with black references. therefore, dc coupled is not recommended for ccd applications. offset control dac the offset dac is controlled by 8-bits. the offset range is 480 mv ranging from -120 mv to +300 mv (when db5 is set to 0) and -240 mv to +240 mv (when db5 is set to 1). therefore, the resolution of the 8-bit offset dac is 1.88 mv. however, the xrd98l23 has +/- 60 mv reserved for internal offsets. therefore, the effective range for adjusting for cis offsets or black reference is 300 mv. the offset adjustment is used primarily to correct for the difference between the black level of the image sensor and the bottom ladder reference voltage (vrb) of the adc. by adjusting the black level to correspond to vrb, the entire range of the adc can be used. if the offset of the cis output is greater than 300 mv an external reference can be applied to vdcext. the external reference can be used to adjust for large offsets only when the internal mode is configured through the serial port. since the offset dac adjustment is done before the gain stage, it is gain-dependent. for example, if the gain needs to be changed between lines (red to blue, etc.), the offset is calibrated before the signal passes through the pga. pga (programmable gain amplifier) dac the gain of the input waveform is controlled by a 6-bit pga. the pga is used along with the offset dac for the purpose of using the entire range of the adc. the pga has a linear gain from 1 to 10. figure 20, is a plot of the transfer curve for the pga gain. pga gain transfer curve gain 1 - 10 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 code gain figure 21. transfer curve for the 6-bit pga after the signal is level shifted to correspond with the bottom ladder reference voltage, the system can be calibrated such that a white video pixel can represent the top ladder reference voltage to the adc. this allows for a full scale conversion maximizing the resolution of the adc. analog to digital converter the adc is an 8-bit, 10 msps analog-to-digital con- verter for high speed and high accuracy. the adc uses a subranging architecture to maintain low power con- sumption at high conversion rates. the output of the adc is on 8-bit databus. adcclk samples the input on its falling edge. after the input is sampled, the data is latched to the output drivers. on the rising edge of the adcclk, invalid data is latched to the output drivers. there is an 8 clock cycle latency (config 00, 11) or 6 pixel count latency (config 01, 10) for the analog-to-digital converter. the v rt and v rb reference voltages for the adc are generated internally, unless the external v rt is se- lected. in the external v rt mode, the v rt voltage is set through the vref+ pin. this allows the user to select the dynamic range of the adc.
xrd98l23 28 rev. 1.00 serial load control registers the serial load registers are controlled by a three wire serial interface through the bi-directional parallel port to reduce the pin count of this device. when synch is set to high, the output bus is tri-stated and the serial interface is activated. db7/ld, db5/sclk and db6/ sdata are the three input signals that control this process. the db7/ld signal is set low to initiate the loading of the internal registers. there are internal registers that are accessed via an 11- bit data string. data is shifted in on the rising edge of sclk and loaded to the registers on the rising edge of ld. the data on pin db6/sdata is latched automati- cally after eleven db5/sclks have been counted. if eleven clocks are not present on db5/sclk before the db7/ld signal returns high, no data will be loaded into the internal registers. if more than 11 clocks are present on db5/sclk, the additional clocks will be ignored. the data corresponding to the first eleven db5/sclks will be loaded only. the first three msbs choose which internal register will be selected. the remaining 8 lsbs contain the data needed for programming the internal register for a particular configuration. power-up state of the internal registers the control register settings upon initial power-up are for cis, dc coupled configuration (v rt is set to internal, input dc reference=agnd and the input to the adc is selected through the red channel). gain is unity and offset is set to zero. the test modes are disabled in the power-up state. db6/sdata db5/sclk synch s2 s1 s0 d7 d2 d1 d0 db7/ld tdl tdz tsclkw tds tdh figure 22. write timing
xrd98l23 29 rev. 1.00 note : these are the control register settings upon initial power-up. the previous register settings are retained following a logic power-down initiated by the power down bit except the signal configuration. when de-selecting the power down bit (d7 = 0, normal), the signal configuration (d5 and d0) has to be reprogrammed. function (register s2/s1/s0) d7 d6 d5 d4 d3 d2 d1 d0 power-up state (note 1) red gain g5 g4 g3 g2 g1 g0 x x 000000xx (000) (msb) (lsb) red offset o7 o6 o5 o4 o3 o2 o1 o0 01000000 (001) (msb) (lsb) grn gain g5 g4 g3 g2 g1 g0 x x 000000xx (010) (msb) (lsb) grn offset (011) o7 o6 o5 o4 o3 o2 o1 o0 01000000 (msb) (lsb) blu gain (100) g5 g4 g3 g2 g1 g0 x x 000000xx (msb) (lsb) blu offset (101) o7 o6 o5 o4 o3 o2 o1 o0 01000000 (msb) (lsb) mode power digital v rt input dc dc/ac signal signal 00000000 (110) down reset reference polarity configuration (v dcref ) 0: normal 0: no reset 0: internal 0: internal 0: dc 0: non- 00: single-channel (v dcref =agnd) inverted red input/gain/offset 1: 1:reset 1: external 1: external 1: ac (cis) power (registers (v dcref =v dcext ) 1: inverted 01: single-channel down are reset to (ccd/cis) red input power-up red/grn/blu states) gain/offset cycle pixel-by-pixel or dual channel red/grn 10: triple-channel red/grn/blu input/gain/offset cycle pixel-by-pixel 11: triple-channel red/grn/blu input/gain/offset cycle line-by-line mode output output offset internal cis test4 test3 test2 test1 00000000 &test bus disable dac reference (111) control range circuit must be 0:outputs 0:-120mv to 0:normal 0: test4 0: test3 0: test2 0:normal programmed enabled +360mv disabled disabled disabled to 1 1:outputs 1:-280mv to 1:reference 1: output 1: output 1: input 1: test1 disabled +240mv circuit of buffer of pga of adc enabled enabled tied to tied to tied to blu vdcext grn control registers
xrd98l23 30 rev. 1.00
xrd98l23 31 rev. 1.00 20 lead shrink small outline package (5.3 mm ssop) rev. 2.00 20 11 10 e d e h b a l c a 1 seating plane a a 2 1 inches millimeters symbol min max min max a 0.067 0.079 1.70 2.00 a1 0.002 0.006 0.05 0.15 a2 0.065 0.073 1.65 1.85 b 0.009 0.015 0.22 0.38 c 0.004 0.010 0.09 0.25 d 0.272 0.296 6.90 7.50 e 0.197 0.221 5.00 5.60 e 0.0256 bsc 0.65 bsc h 0.292 0.323 7.40 8.20 l 0.022 0.037 0.55 0.95 a 0 8 0 8 note: the control dimension is the inch column
xrd98l23 32 rev. 1.00 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2000 exar corporation datasheet november 2002 reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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